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preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. june 2006 rev 1 1/22 1 m36l0r7060u1 m36l0r7060l1 m36l0r7050u1 m36l0r7050l1 128 mbit (mux i/o, multiple bank , multi-level, burst) flash memory, 32 or 64 mbit psram, 1. 8v supply multi-chip package feature summary multi-chip package ? 1 die of 128 mbit (8mb x16, mux i/o multiple bank, multi-level, burst) flash memory ? 1 die of 32 or 64mbit mux i/o, burst pseudo sram supply voltage ?v ddf = v ddp = v ddqf = 1.7 to 1.95v ?v ppf = 9v for fast program electronic signature ? manufacturer code: 20h ? device codes (top flash configuration): m36l0r7060u1: 882eh, m36l0r7050u1: 882eh ? device codes (bottom flash configuration) m36l0r7060l1: 882fh m36l0r7050l1: 882fh ecopack? package flash memory multiplexed address/data synchronous / asynchronous read ? synchronous burst read mode: 66mhz ? random access: 85ns synchronous burst read suspend programming time ? 10s typical word program time using buffer enhanced factory program command memory organization ? multiple bank memory array: 8 mbit banks ? parameter blocks (top or bottom location) security ? 64 bit unique device number ? 2112 bit user programmable otp cells 100,000 program/erase cycles per block dual operations ? program/erase in one bank while read in others ? no delay between read and write operations block locking ? all blocks locked at power-up ? any combination of blocks can be locked with zero latency ?wp f for block lock-down ? absolute write protection with v ppf = v ss common flash interface (cfi) psram access time: 70ns synchronous modes: ? synchronous write: continuous burst ? synchronous read: continuous burst or fixed length: 4, 8 or 16 words for 32 mbit devices or 4, 8,16 or 32 words for 64 mbit devices ? maximum clock frequency: 83mhz low power consumption low power features ? partial array self-refresh (pasr) ? deep power-down (dpd) mode ? automatic temperature-compensated self- refresh tfbga88 (zam) 8 x 10mm fbga www.st.com
contents m36l0r7060u1, m36l0r7060l1, m36l0r7050u1, m36l0r7050l1 2/22 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 address inputs (adq0-adq15 and a16-a22) . . . . . . . . . . . . . . . . . . . . . 10 2.2 data input/output (adq0-adq15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 latch enable (l ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 clock (k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5 wait (wait) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6 flash memory chip enable (e f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.7 flash memory output enable (g f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.8 flash memory write enable (w f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.9 flash memory write protect (wp f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.10 flash memory reset (rp f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.11 psram chip enable (e p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.12 psram output enable (g p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.13 psram write enable (w p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.14 psram upper byte enable (ub p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.15 psram lower byte enable (lb p ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.16 psram configuration register enable (cr p ) . . . . . . . . . . . . . . . . . . . . . 12 2.17 v ddf flash memory supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.18 v ccp psram supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.19 v ddqf supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.20 v ppf flash memory program supply voltage . . . . . . . . . . . . . . . . . . . . . 13 2.21 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.22 v ssq ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
m36l0r7060u1, m36l0r7060l1, m36l0r7050u1, m36l0r7050l1 contents 3/22 6 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
list of tables m36l0r7060u1, m36l0r7060l1, m36l0r7050u1, m36l0r7050l1 4/22 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. operating modes - standard asynchronous operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5. device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 6. stacked tfbga88 8 10mm - 8 10 active ball array, 0.8mm pitch, package data . . . . 19 table 7. part numbering scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
m36l0r7060u1, m36l0r7060l1, m36l0r7050u1, m36l0r7050l1 list of figures 5/22 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. tfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 figure 5. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 6. tfbga88 8 10mm, 8 10 ball array - 0.8mm pitch, bottom view package outline. . . . . 19
summary description m36l0r7060u1, m36l0r7060l1, m36l0r7050u1, m36l0r7050l1 6/22 1 summary description the m36l0r7060u1, m36l0r7060l1, m36l0r7050u1 and m36l0r7050l1 combine two memory devices in a multi-chip package: a 128-mbit, multiple bank flash memory, the m58lr128g(u/l) a 32 or 64 mbit pseudosram, the m69km048aa or m69km096aa, respectively. the purpose of this document is to describe how the two memory components operate with respect to each other. it must be read in conjunction with the m58lrxxxgul and m69km048aa or m69km096aa datasheets, where all specifications required to operate the flash memory and psram components are fully detailed. these datasheets are available from the stmicroelectronics website: www.st.com . recommended operating conditions do not allow more than one memory to be active at the same time. the memory is offered in a stacked tfbga88 (8 10mm, 8 10 ball array, 0.8mm pitch) package. in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second-level interconnect. the category of second-level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com .
m36l0r7060u1, m36l0r7060l1, m36l0r7050u1, m36l0r7050l1 summary description 7/22 figure 1. logic diagram ai12016 23 a16-a22 adq0-adq15 m36l0r7060u1 m36l0r7060l1 m36l0r7050u1 m36l0r7050l1 g f 16 w f rp f wp f e p g p w p ub p lb p v ss v ddf v ppf v ddp wait l k v ddqf e f cr p
summary description m36l0r7060u1, m36l0r7060l1, m36l0r7050u1, m36l0r7050l1 8/22 table 1. signal names a16-a22 (1), (2) 1. a16-a20 (in the case of a 32mb psram) or a16-a21 (in the case of a 64mb psram) are common to the flash memory and the psram 2. a21-a22 (if the mcp contains a 32mb psram) or a 22 (if the mcp contains a 64mb psram) are address input(s) for the flash memory component only. address inputs adq0-adq15 flash memory and psram common data input/outputs, address inputs or command inputs v ddf power supply for flash memory v ddqf flash memory power supply for i/o buffers v ppf flash memory optional supply voltage for fast program and erase v ss ground v ddp psram power supply nc not connected internally du do not use as internally connected wait flash memory and psram common wait data in burst mode l flash memory and psram latch enable input k flash memory and psram burst clock flash memory e f chip enable input g f output enable input w f write enable input rp f reset input wp f write protect input psram e p chip enable input g p output enable input w p write enable input cr p configuration register enable input ub p upper byte enable input lb p lower byte enable input
m36l0r7060u1, m36l0r7060l1, m36l0r7050u1, m36l0r7050l1 summary description 9/22 figure 2. tfbga connections (top view through package) 8 7 6 5 4 3 2 1 c b a21 k nc nc d e f du du w f v ss a19 a18 a22 nc nc v ss nc lb p nc nc nc v ppf nc a17 nc a20 nc nc l wp f nc nc nc nc nc a16 rp f ub p nc wait adq13 nc adq5 adq10 adq2 adq8 adq7 adq14 g p adq12 adq3 adq1 adq0 adq15 adq6 adq4 adq11 adq9 g f v ddqf e f cr p v ddp v ss v ss v ss v ss v ss v ddf v ddqf v ss du du du du du du a g h j k ai12017b l m v ddf nc w p e p nc nc du du nc nc nc nc v ddqf
signal descriptions m36l0r7060u1, m36l0r7060l1, m36l0r7050u1, m36l0r7050l1 10/22 2 signal descriptions see figure 1: logic diagram and table 1: signal names , for a brief overview of the signals connected to this device. 2.1 address inputs (a dq0-adq15 and a16-a22) adq0-adq15 and a16-a20 (for the m36l0r7050u1/l1) or a16-a21 (for the m36l0r7060u1/l1) are common to the flash memory and psram components. in the flash memory, the address inputs select the cells in the array to access during bus read operations. during bus write operations they control the commands sent to the command interface of the program/erase controller. in the psram, the address inputs a16-a20 (/a21) are used in conjunction with adq0 to adq15, to select the cells in the memory array that are accessed during read and write operations. 2.2 data input/output (adq0-adq15) the data i/o output the data stored at the selected address during a bus read operation or input a command or the data to be programmed during a bus write operation. 2.3 latch enable (l ) the latch enable input is common to the flash memory and psram components. for details of how the latch enable signal behaves, please refer to the datasheets of the respective memory components: m69km048aa or m69km096aa for the psram and m58lrxxxgul for the flash memory. 2.4 clock (k) the clock input is common to the flash memory and psram components. for details of how the clock signal behaves, please refer to the datasheets of the respective memory components: m69km048aa or m69km096aa for the psram and m58lrxxxgul for the flash memory. 2.5 wait (wait) the wait output is common to the flash memory and psram components. for details of how the wait signal behaves, please refer to the datasheets of the respective memory components: m69km048aa or m69km096aa for the psram and m58lrxxxgul for the flash memory
m36l0r7060u1, m36l0r7060l1, m36l0r7050u1, m36l0r7050l1 signal descriptions 11/22 2.6 flash memory chip enable (e f ) the chip enable input activates the memory control logic, input buffers, decoders and sense amplifiers. when chip enable is at v il and reset is at v ih the device is in active mode. when chip enable is at v ih the memory is deselected, the outputs are high impedance and the power consumption is reduced to the stand-by level. it is not allowed to set both e f and e p to v il at the same time. 2.7 flash memory output enable (g f ) the output enable input controls data outputs during the bus read operation of the flash memory. 2.8 flash memory write enable (w f ) the write enable input controls the bus write operation of the flash memory?s command interface. the data and address inputs are latched on the rising edge of chip enable or write enable whichever occurs first. 2.9 flash memory write protect (wp f ) write protect is an input that gives an additional hardware protection for each block. when write protect is at v il , the lock-down is enabled and the protection status of the locked- down blocks cannot be changed. when write protect is at v ih , the lock-down is disabled and the locked-down blocks can be locked or unlocked. (refer to m58lrxxxgul datasheet). 2.10 flash memory reset (rp f ) the reset input provides a hardware reset of the memory. when reset is at v il , the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the reset supply current i dd2 . refer to the m58lrxxxgul datasheet for the value of i dd2. after reset all blocks are in the locked state and the configuration register is reset. when reset is at v ih , the device is in normal operation. exiting reset mode the device enters asynchronous read mode, but a negative transition of chip enable or latch enable is required to ensure valid data outputs. the reset pin can be interfaced with 3v logic without any additional circuitry. it can be tied to v rph (refer to the m58lrxxxgul datasheet). 2.11 psram chip enable (e p ) chip enable, e p , activates the device when driven low (asserted). when de-asserted (v ih ), the device is disabled and goes automatically in low-power standby mode or deep power- down mode, accordin g to the rcr settings. it is not allowed to set both e f and e p to v il at the same time.
signal descriptions m36l0r7060u1, m36l0r7060l1, m36l0r7050u1, m36l0r7050l1 12/22 2.12 psram output enable (g p ) when held low, v il , the output enable, g p , enables the bus read operations of the memory. 2.13 psram write enable (w p ) write enable, w p , controls the bus write operation of the memory. when asserted (v il ), the device is in write mode and write operations can be performed either to the configuration registers or to the memory array. 2.14 psram upper byte enable (ub p ) the upper byte enable, ub p , gates the data on the upper byte of the address inputs/ data inputs/outputs (adq8-adq15) to or from the upper part of the selected address during a write or read operation. 2.15 psram lower byte enable (lb p ) the lower byte enable, lb p , gates the data on the lower byte of the address inputs/data input/outputs (adq0-adq7) to or from the lower part of the selected address during a write or read operation. if both lb p and ub p are disabled (high), the device will di sable the data bus from receiving or transmitting data. although the device will seem to be deselected, it remains in an active mode as long as e p remains low. 2.16 psram configuration register enable (cr p ) when this signal is driven high, v ih , bus read or write operations access either the value of the refresh configuration register (rcr) or the bus configuration register (bcr) according to the value of a19. 2.17 v ddf flash memory supply voltage v ddf provides the power supply to the internal core of the flash memory. it is the main power supply for all flash memory operations (read, program and erase). 2.18 v ccp psram supply voltage the v ccp supply voltage is th e core supply voltage.
m36l0r7060u1, m36l0r7060l1, m36l0r7050u1, m36l0r7050l1 signal descriptions 13/22 2.19 v ddqf supply voltage v ddqf provides the power supply to the i/o pins and enables all outputs to be powered independently of v ddf . v ddqf can be tied to v ddf or can use a separate supply. 2.20 v ppf flash memory program supply voltage v ppf is both a control input and a power supply pin. the two functions are selected by the voltage range applied to the pin. if v ppf is kept in a low voltage range (0v to v ddqf ) v ppf is seen as a control input. in this case a voltage lower than v pplk gives absolute protection against program or erase, while v ppf in the v pp1 range enables these functions (see the m58lrxxxgul datasheet for the relevant values). v ppf is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. if v ppf is in the range of v pph it acts as a power supply pin. in this condition v ppf must be stable until the program/erase algorithm is completed. 2.21 v ss ground v ss ground is the common flash memory and psram ground. it is the reference for the core supplies. it must be connected to the system ground. 2.22 v ssq ground v ssq ground is the reference for the input/output circuitry driven by v ddqf . v ssq must be connected to v ss note: each device in a system should have v ddf , v ddqf and v pp decoupled with a 0.1f ceramic capacitor close to the pin (high frequency, inhere ntly low inductance capacitors should be as close as possible to the package). see figure 5: ac measurement load circuit . the pcb track widths should be sufficient to carry the required v pp program and erase currents.
functional description m36l0r7060u1, m36l0r7060l1, m36l0r7050u1, m36l0r7050l1 14/22 3 functional description the psram and flash memory components have separate power supplies but share the same grounds. they are distinguished by two chip enable inputs: e f for the flash memory and e p for the psram. recommended operating conditions do not allow more than one device to be active at a time. the most common example is simultaneo us read operations on one of the flash memory and the psram components which would result in a data bus contention. therefore it is recommended to put the other devices in the high impedance state when reading the selected device. figure 3. functional block diagram 1. address inputs corresponding to the m36l0r7050u1 and m36l0r7050l1 devices. 2. address inputs corresponding to the m36l0r7060u1 and m36l0r7060l1 devices. ai12335 e p cr p g p w p adq0-adq15 v ppf a16-a20 (1) or a16-a21 (2) a21-a22 (1) or a22 (2) 32 mbit or 64 mbit psram g f ub p lb p wait k v ddqf v ss 128 mbit flash memory v ddf v ccp l rp f wp f w f e f
m36l0r7060u1, m36l0r7060l1, m36l0r7050u1, m36l0r7050l1 functional description 15/22 table 2. operating modes - standard asynchronous operation operation (1) (2) e f g f w f rp f wait (3) l e p w p g p ub p lb p cr p a19 a18 other address inputs adq0- adq7 adq8- adq15 flash memory bus read v il v il v ih v ih v ih the psram must be disabled. data output bus write v il v ih v il v ih v ih data input address latch v il v ih xv ih v il address input output disable v il v ih v ih v ih v ih any psram mode is allowed. hi-z standby v ih xxv ih hi-z x hi-z reset x x x v il hi-z x hi-z psram word read the flash memory must be disabled. \_/ v il v ih v il v il v il v il address in valid address in/ data out valid word write v il v ih v il v il v il address in valid address in/ data in valid read configuration register (cr controlled method) (4) v ih v il v il v il v ih 00(rcr) 10(bcr) x1(didr) x address in/ bcr, rcr or didr content valid program configuration register (cr controlled) (5) v il v il v ih xx 0 or 00 (rcr) 1 or 10 (bcr) (6) bcr/ rcr data address in valid output disable/no operation any flash memory mode is allowed. x v ih xx x v il x x x high-z deep power- down (7) v ih x x x x x x x x high-z standby v ih xx x x x v il x x high-z 1. the clock signal, k, must remain low when the psram is operating in asynchronous mode. 2. x = don?t care 3. in the flash memory the wait signal polarity is configured using the set configuration register command. 4. operating mode available in the m36l0r7060u1 and m36l0r7060l1 only (see m69km096aa datasheet). 5. bcr and rcr only. 6. in the psram of the m36l0r7050u1 and m36l0r7050l1, a19 is used to select between the bcr and the rcr whereas in the psram of the m36l0r7060u1 and m36l0r7060l1 both a18 and a19 are used to select the bcr, the rcr or the didr. 7. the device enters deep power-down mode by driving the chip enable signal, e , from low to high, with bit 4 of the rcr set to ?0?. the device remains in deep power-down mode until e goes low again and is held low for t eleh(dp) .
maximum rating m36l0r7060u1, m36l0r7060l1, m36l0r7050u1, m36l0r7050l1 16/22 4 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 3. absolute maximum ratings symbol parameter value unit min max t a ambient operating temperature ?25 85 c t bias temperature under bias ?25 85 c t stg storage temperature ?55 125 c v io input or output voltage ?0.2 2.45 v v ddf , v ddqf v ccp core and input/output supply voltages ?0.2 2.45 v v ppf flash program voltage ?0.2 10 v i o output short circuit current 100 ma t vppfh time for v ppf at v ppfh 100 hours
m36l0r7060u1, m36l0r7060l1, m36l0r7050u1, m36l0r7050l1 dc and ac parameters 17/22 5 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 4: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. figure 4. ac measurement i/o waveform table 4. operating and ac measurement conditions parameter flash memory psram unit min max min max v ddf supply voltage 1.7 1.95 ? ? v v ccp supply voltage ? ? 1.7 1.95 v v ddqf supply voltage 1.7 1.95 ? ? v v ppf supply voltage (factory environment) 8.5 9.5 ? ? v v ppf supply voltage (application environment) ?0.4 v ddqf +0.4 ??v ambient operating temperature ?25 85 ?25 85 c load capacitance (c l )3030pf output circuit resistors (r 1 , r 2 ) 16.7 16.7 k ? input rise and fall times 5 2 ns input pulse voltages 0 to v ddqf 0 to v ccp /2 v input and output timing ref. voltages v ddqf /2 v ccp /2 v ai06161b v ddqf 0v v ddqf /2
dc and ac parameters m36l0r7060u1, m36l0r7060l1, m36l0r7050u1, m36l0r7050l1 18/22 figure 5. ac measurement load circuit please refer to the m58lrxxxgul and m6 9km048aa or m69km096aa datasheets for further dc and ac characteristics values and illustrations. table 5. device capacitance symbol parameter test condition min max (1) 1. sampled only, not 100% tested. unit c in input capacitance v in = 0v 14 pf c out output capacitance v out = 0v 18 pf ai08364c v ddqf c l c l includes jig capacitance r 1 device under test 0.1f v ddqf r 2 0.1f v ddf
m36l0r7060u1, m36l0r7060l1, m36l0r7050u1, m36l0r7050l1 package mechanical 19/22 6 package mechanical figure 6. tfbga88 8 10mm, 8 10 ball array - 0.8mm pitch, bottom view package outline 1. drawing is not to scale. table 6. stacked tfbga88 8 10mm - 8 10 active ball array, 0.8mm pitch, package data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.200 0.0079 a2 0.850 0.0335 b 0.350 0.300 0.400 0.0138 0.0118 0.0157 d 8.000 7.900 8.100 0.3150 0.3110 0.3189 d1 5.600 0.2205 ddd 0.100 0.0039 e 10.000 9.900 10.100 0.3937 0.3898 0.3976 e1 7.200 0.2835 e2 8.800 0.3465 e 0.800 ? ? 0.0315 ? ? fd 1.200 0.0472 fe 1.400 0.0551 fe1 0.600 0.0236 sd 0.400 0.0157 se 0.400 0.0157 a2 a1 a bga-z42 ddd d e e b se fd e2 d1 sd ball "a1" e1 fe fe1
part numbering m36l0r7060u1, m36l0r7060l1, m36l0r7050u1, m36l0r7050l1 20/22 7 part numbering note: devices are shipped from the factory with the memory content bits, in valid blocks, erased to ?1?. for further information on any aspect of this device, please contact your nearest st sales office. table 7. part numbering scheme example: m36 l 0 r 7 0 5 0 l 1 zam f device type m36 = multi-chip package (flash + ram) flash 1 architecture l = multi-level, multiple bank, burst mode flash 2 architecture 0 = no die operating voltage r = v ddf = v ddp = v ddqf = 1.7v to 1.95v flash 1 density 7 = 128 mbit flash 2 density 0 = no die ram 1 density 5 = 32 mbit 6 = 64 mbit ram 2 density 0 = no die parameter block location u = top boot block flash l = bottom boot block flash product version 1 = 0.13m flash technology and multilevel design, 85ns speeds; ram, 70ns speed mux i/o package zam = stacked tfbga88 8x10mm - 8x10 active ball array, 0.8mm pitch packing option e = ecopack? package, standard packing f = ecopack? package, tape & reel packing
m36l0r7060u1, m36l0r7060l1, m36l0r7050u1, m36l0r7050l1 revision history 21/22 8 revision history table 8. document revision history date revision changes 08-jun-2006 1 initial release.
m36l0r7060u1, m36l0r7060l1, m36l0r7050u1, m36l0r7050l1 22/22 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorize representative of st, st products are not designed, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems, where failure or malfunction may result in personal injury, death, or severe property or environmental damage. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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